The present invention relates to a semiconductor device containing circuit elements operated with a plurality of power supplies, such as a non-volatile memory, and a method of manufacturing the semiconductor device.
Generally, when data are written in or erased from a non-volatile memory, a power supply of about 12V, which is higher than that in a usual reading operation, is used. For this reason, circuits for transacting the writing and erasing operations require circuit elements of a high breakdown voltage which are capable of withstanding the high voltage. In contrast, a power supply of about 3.3V is used for performing the usual reading operation. Accordingly, a circuit only for transacting the reading operation requires no high-breakdown-voltage elements, but is satisfied with low-breakdown-voltage elements. As a result, in the non-volatile memory, high-breakdown-voltage elements and low-breakdown-voltage elements are mixedly present in one semiconductor device, i.e., a semiconductor chip.
On the other hand, a conventional logic device generally employs a power supply of 3.3V, and does not need such a high voltage as used in the non-volatile memory. Namely, hardly any high-breakdown-voltage elements are used in this device.
In recent years, demand for a logic device containing non-volatile memory cells is increasing in the market. Such a logic device, therefore, mixedly contains low-breakdown-voltage elements and the non-volatile memories having high-breakdown-voltage elements.
Generally, a MOSFET arranged in the logic device containing non-volatile memory cells adopts an LDD (Lightly Doped Drain) structure in order to prevent its reliability from lowering due to hot carriers (Reference Publication: Takeda, "Hot Carrier Effect", Nikkei-McGraw-Hill). With the LDD structure, it is possible not only to reduce the deterioration due to the hot carrier effect, but also to relax the electric field at the drain edge portion. Accordingly, the LDD structure is well-known as an indispensable technique for realizing a high-breakdown-voltage element.
In order to attain a preferable breakdown voltage in an LDD structure, an LDD portion, which is formed in a drain layer near an edge of the gate electrode and has a low carrier-impurity concentration, i.e., an increased resistivity, should have a sufficiently low concentration and a sufficiently large length (LDD length). The LDD length means the length of the LDD portion extending in the channel-length direction from the edge of the gate electrode. Where the length is large enough, it is possible to maintain a sufficiently low LDD concentration. For this reason, a high-breakdown-voltage element is provided with an LDD portion having a large LDD length and a low concentration of, e.g., 1.times.10.sup.18 /cm.sup.3, which is lower than a generally used concentration of about 1.times.10.sup.19 /cm.sup.3. Such an LDD portion of a low concentration will be referred to as N.sup.-- -LDD or P.sup.-- -LDD.
On the other hand, an LDD structure is adopted in a low-breakdown-voltage element to ensure reliability in relation to hot carriers. However, unlike the high-breakdown-voltage element, the low-breakdown-voltage element is provided with an LDD portion having a generally used concentration of about 1.times.10.sup.19 /cm.sup.3. Such an LDD portion of a generally used concentration will be referred to as N.sup.- -LDD or P.sup.- -LDD. This is because, as is clear from FIGS. 10A and 10B which show dependency of the breakdown voltage BV and electric current (transistor-channel current) Id on LDD concentration in N-channel MOSFETs, the impurity concentration of an LDD portion has a great influence on the transistor-channel current Id. Specifically, a decrease in the impurity concentration in an LDD portion directly increases its parasitic resistance and lowers the channel current Id. Further, as the LDD length of the LDD portion is shorter, its parasitic resistance becomes smaller. For this reason, an LDD transistor of a side wall type is widely used as a structure for ensuring a small LDD length with a high controllability.
The above described explanation relates to general structures of high-breakdown-voltage and low-breakdown-voltage MOSFETs. As a method of manufacturing a semiconductor device mixedly containing these two types of MOSFETs, i.e., high-breakdown-voltage and low-breakdown-voltage MOSFETs, there is a conventional method shown in FIGS. 11A to 12B.
First, as shown in FIG. 11A, an N-well layer 402 for arranging a P-channel MOSFET, i.e., PMOSFET, in a P-semiconductor substrate 401, a silicon oxide film 403, a gate oxide film 404, and a gate electrode and wiring layer 405 are formed in this order by conventional steps. Then, a resist pattern 406 is formed to have an opening at a position corresponding to an N-channel MOSFET, i.e., NMOSFET, in a low-breakdown-voltage-element area LBA. Then, using the resist pattern 406 as a mask, an impurity for forming an N.sup.- -LDD portion of the low-breakdown-voltage NMOSFET is ion-implanted.
Subsequently, the resist pattern 407 is removed, and, as shown in FIG. 11B, a resist pattern 407 is formed to have an opening at a position corresponding to an NMOSFET in a high-breakdown-voltage-element area HBA. Then, using the resist pattern 407 as a mask, an impurity for forming an N.sup.-- -LDD portion of the high-breakdown-voltage NMOSFET is ion-implanted. The impurity concentration of the N.sup.-- -LDD portion of the high-breakdown-voltage NMOSFET is set to be lower than that of the N.sup.- -LDD portion of the low-breakdown-voltage NMOSFET.
Following the steps for the NMOSFETs and similarly thereto, impurities for forming LDD portions of PMOSFETs are separately ion-implanted to obtain different concentrations for the low- and high-breakdown-voltage sides, though detailed drawings showing these steps are omitted.
After that, as shown in FIG. 12A, side walls 410 are formed on the gate electrode 405. Then, a resist pattern 411 is formed to at least partly cover a position corresponding to a drain N.sup.-- -LDD portion of the high-breakdown-voltage NMOSFET. Then, using the resist pattern 411 as a mask, an impurity for forming N.sup.+ -diffusion layers is ion-implanted in the semiconductor substrate 401.
Similarly to the NMOSFETS, an impurity for forming P.sup.+ -diffusion layers of the PMOSFET is ion-implanted through a mask which at least partly covers a position corresponding to a drain P.sup.-- -LDD portion of the high-breakdown-voltage PMOSFET.
Subsequently, the substrate 401 is post-oxidized, so that an oxide film 413 is formed on the exposed surfaces of the substrate 401, and the ion-implanted impurities are diffused and activated to complete the drain and source layers of the MOSFETs. As a result, a structure shown in FIG. 12B is obtained.
In the structure shown in FIG. 12B, the drain layer of the high-breakdown-voltage NMOSFET is provided with the LDD portion having a relatively large LDD length, which has been given by the resist pattern 441. Further, the impurity doping, i.e., ion-implantation, for forming the drain N.sup.-- -LDD portion, which has a relatively low concentration, of the high-breakdown-voltage NMOSFET, can be selectively performed through the resist pattern 407.
On the other hand, the impurity doping, i.e., ion-implantation, for forming the N.sup.- -LDD portions, which have a middle concentration, of the low-breakdown-voltage NMOSFET, can be selectively performed through the resist pattern 406. Since their LDD length is decided by the side walls 410 formed on the sides of the gate electrode, a small LDD length is obtained under high accurate control. As a result, the LDD portions of the low-breakdown-voltage NMOSFET can have a concentration relatively high enough to ensure reliability in relation to hot carriers, and further can have a small LDD length, so that the transistor is provided with a high reliability and a high channel current Id.
However, in the semiconductor device manufactured by the above described conventional method, an LDD portion 416 having a low concentration is formed on the source side of the high-breakdown-voltage MOSFET, where it does not work for the breakdown voltage (see FIG. 13 which shows a portion surrounded by a broken line in FIG. 12B). Since the LDD portion 416 is formed to have a very low concentration for ensuring a high breakdown voltage, it affects the MOSFET and deteriorates its channel current. As a result, the high-breakdown-voltage MOSFET cannot be driven at a high speed.
In order to solve this problem, there is a known method in which an N.sup.+ -impurity is ion-implanted at a high concentration only into the source layer of the high-breakdown-voltage NMOSFET (a P.sup.+ -impurity for the PMOSFET) in advance of the formation of the side walls 410. In this case, an N.sup.+ -impurity is ion-implanted at a high concentration into the drain layer of the high-breakdown-voltage NMOSFET and the drain and source layer of the low-breakdown-voltage NMOSFET (a P.sup.+ -impurity for the PMOSFETs) after the formation of the side walls 410, as in the method shown in FIGS. 11A to 12B. The high-breakdown-voltage MOSFET thus formed has a structure shown in FIG. 14, in which the end of the source layer has an enough increased impurity concentration, i.e., an decreased resistivity, to ignore its parasitic resistance. Further, on the other hand, the drain layer has an LDD portion of a large enough LDD length and a low enough impurity concentration to ensure a high breakdown voltage. As a result, the high-breakdown-voltage element is formed while its channel current is prevented from lowering, as far as possible.
However, in order to form the structure shown in FIG. 14, it is inevitably necessary to ion-implant an N.sup.+ -impurity at a high concentration into the source layer of the high-breakdown-voltage NMOSFET (a P.sup.+ -impurity for the PMOSFET) in advance, and thus to add a mask step and an ion-implantation step. For example, where the structure shown in FIG. 14 is adopted for both of the NMOSFET and the PMOSFET, it is necessary to add a mask step and an ion-implantation step for ion-implanting an N.sup.+ -impurity, and a mask step and an ion-implantation step for ion-implanting a P.sup.+ -impurity, as compared to the structure shown in FIG. 13. Accordingly, the manufacturing cost is seriously increased due to the added steps.
To reiterate, the conventional technique described above with reference to FIGS. 11A to 13 entails a problem such that a high-breakdown-voltage element lowers its performance to a great extent and hinders a semiconductor device in operating at a high speed. On the other hand, the conventional technique described above with reference to FIG. 14 entails a problem such that its complicated process increases the cost of manufacturing a semiconductor device.